? semiconductor components industries, llc, 2014 december, 2014 ? rev. 0 1 publication order number: nvlus4c12n/d nvlus4c12n power mosfet 30 v, 10.7 a, single n?channel, 2.0x2.0x0.55 mm cool udfn6 package features ? low profile udfn 2.0 x 2.0 x 0.55 mm for board space saving with exposed drain pads for excellent thermal conduction ? ultra low r ds(on) to reduce conduction losses ? optimized gate charge to reduce switching losses ? low capacitance to minimize driver losses ? nv prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant applications ? power load switch ? synch dc?dc converters ? wireless charging circuit maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value unit drain-to-source voltage v dss 30 v gate-to-source voltage v gs 20 v continuous drain current (note 1) steady state t a = 25 c i d 10.7 a t a = 85 c 7.7 t 5 s t a = 25 c 15.1 power dissipa- tion (note 1) steady state t a = 25 c p d 1.54 w t 5 s t a = 25 c 3.1 continuous drain current (note 2) steady state t a = 25 c i d 6.8 a t a = 85 c 4.9 power dissipation (note 2) t a = 25 c p d 0.63 w pulsed drain current t p = 10 s i dm 43 a mosfet operating junction and storage temperature t j , t stg -55 to 150 c source current (body diode) (note 1) i s 1.55 a lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. surface mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [2 oz] including traces). 2. surface-mounted on fr4 board using the minimum recommended pad size, 2 oz. cu. www. onsemi.com n?channel mosfet 30 v 12 m @ 4.5 v 9 m @ 10 v r ds(on) max i d max v (br)dss mosfet udfn6 ( cool ) case 517bg see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information ag = specific device code m = date code = pb?free package agm 1 marking diagram (top view) (note: microdot may be in either location) 10.7 a d s g pin connections pin 1 d s 1 2 3 6 5 4 d d s d d g d s 19 m @ 3.3 v 15 m @ 3.7 v
nvlus4c12n www. onsemi.com 2 thermal resistance ratings parameter symbol max unit junction-to-ambient ? steady state (note 3) r ja 81 c/w junction-to-ambient ? t 5 s (note 3) r ja 40.5 junction-to-ambient ? steady state min pad (note 4) r ja 200 3. surface-mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [2 oz] including traces). 4. surface-mounted on fr4 board using the minimum recommended pad size, 2 oz. cu. electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max units off characteristics drain-to-source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain-to-source breakdown voltage temperature coefficient v (br)dss /t j i d = 250 a, ref to 25 c 12 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1.0 a t j = 125 c 10 gate-to-source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.3 2.1 v negative threshold temp. coefficient v gs(th) /t j 4.8 mv/ c drain-to-source on resistance r ds(on) v gs = 10 v, i d = 9.0 a 7.2 9 m v gs = 4.5 v, i d = 8.0 a 9.3 12 v gs = 3.7 v, i d = 5.0 a 10.9 15 v gs = 3.3 v, i d = 5.0 a 13 19 forward transconductance g fs v ds = 15 v, i d = 9.0 a 39 s charges, capacitances & gate resistance input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = 15 v 1172 pf output capacitance c oss 546 reverse transfer capacitance c rss 26 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v; i d = 8.0 a 8.4 nc threshold gate charge q g(th) 1.1 gate-to-source charge q gs 3.0 gate-to-drain charge q gd 2.2 total gate charge q g(tot) v gs = 10 v, v ds = 15 v; i d = 9.0 a 18 nc switching characteristics, vgs = 4.5 v (note 6) turn-on delay time t d(on) v gs = 4.5 v, v dd = 15 v, i d = 8.0 a, r g = 3 9.4 ns rise time t r 15 turn-off delay time t d(off) 14 fall time t f 3.5 switching characteristics, vgs = 10 v (note 6) turn-on delay time t d(on) v gs = 10 v, v dd = 15 v, i d = 9.0 a, r g = 3 6.3 ns rise time t r 14 turn-off delay time t d(off) 18 fall time t f 2.4 5. pulse test: pulse width 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
nvlus4c12n www. onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise specified) parameter units max typ min test condition symbol drain-source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 1.5 a t j = 25 c 0.72 1.1 v t j = 125 c 0.52 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ s, i s = 1.5 a 29 ns charge time t a 14.1 discharge time t b 14.9 reverse recovery charge q rr 20 nc 5. pulse test: pulse width 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures. typical characteristics figure 1. on?region characteristics figure 2. transfer characteristics v ds , drain?to?source voltage (v) v gs , gate?t o?source voltage (v) 1.0 3.0 2.5 2.0 1.5 0.5 0 0 5 10 15 20 25 3.0 2.5 2.0 1.5 1.0 0 5 10 15 20 25 30 35 figure 3. on?resistance vs. gate?to?source voltage figure 4. on?resistance vs. drain current and gate voltage v gs , gate?t o?source voltage (v) i d , drain current (a) 10 9 8 7 6 5 4 3 7 9 11 13 15 17 19 21 8 7 6 5 4 3 2 1 5 7 9 11 13 15 17 i d , drain current (a) i d , drain current (a) r ds(on) , drain?to?source resistance (m ) r ds(on) , drain?to?source resistance (m ) 3.2 ? 10 v t j = 25 c v gs = 2.8 v 2.6 v 2.4 v 2.2 v 3.0 v 2.0 v t j = 25 c t j = 125 c t j = ?55 c v ds = 5 v t j = 25 c i d = 9 a t j = 25 c v gs = 3.3 v 9 v gs = 3.7 v v gs = 4.5 v v gs = 10 v
nvlus4c12n www. onsemi.com 4 typical characteristics figure 5. on?resistance variation with temperature figure 6. drain?to?source leakage current vs. voltage t j , junction temperature ( c) v ds , drain?to?source voltage (v) 125 100 75 50 25 0 ?25 ?50 0.6 0.7 0.9 1.0 1.2 1.3 1.5 1.6 30 25 20 15 10 5 10 100 1000 10,000 figure 7. capacitance variation figure 8. gate?to?source and drain?to?source voltage vs. total charge v ds , drain?to?source voltage (v) q g , total gate charge (nc) 25 20 15 30 10 5 0 0 200 600 800 1000 1400 1600 1800 18 14 12 10 8 4 2 0 0 2 4 6 8 10 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source?to?drain voltage (v) 100 10 1 1 10 100 1000 0.8 0.7 0.6 0.5 0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 r ds(on) , drain?to?source resistance (normalized) i dss , leakage (na) c, capacitance (pf) v gs , gate?t o?source voltage (v) t, time (ns) i s , source current (a) v gs = 10 v i d = 9 a 150 0.8 1.1 1.4 t j = 85 c t j = 125 c t j = 150 c v gs = 0 v t j = 25 c v gs = 0 v 400 1200 c iss c oss c rss t j = 25 c v gs = 10 v v dd = 15 v i d = 8 a 616 q t q gs q gd v dd = 15 v i d = 15 a v gs = 10 v t d(off) t d(on) t r t f t j = 25 c t j = 125 c v gs = 0 v
nvlus4c12n www. onsemi.com 5 typical characteristics figure 11. maximum rated forward biased safe operating area v ds , drain?to?source voltage (v) 100 10 1 0.1 0.01 0.01 0.1 1 10 100 figure 12. thermal response pulse time (sec) 1000 10 1 0.1 0.01 0.001 100 0.01 0.1 1 10 100 i d , drain current (a) r(t) ( c/w) 0.0001 0.00001 0.000001 single pulse 50% duty cycle 20% 10% 5% 2% 1% 0 v < v gs < 10 v t a = 25 c single pulse response dc 10 ms 1 ms r ds(on) limit thermal limit package limit 100 s 10 s device ordering information device package shipping ? NVLUS4C12NTAG udfn6 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nvlus4c12n www. onsemi.com 6 package dimensions notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. center terminal lead is optional. center terminal is connected to terminal lead # 4. 6. leads 1, 2, 5 and 6 are tied to the flag. c seating plane d b e 0.10 c a3 a a1 0.10 c udfn6 2x2, 0.65p case 517bg issue a dim a min max millimeters 0.45 0.55 a1 0.00 0.05 a3 0.13 ref b 0.25 0.35 b1 0.65 bsc d d2 e e2 0.27 bsc e 0.15 ref k l pin one reference 0.08 c 0.10 c note 4 a 0.10 c note 3 l e d2 e2 b b 3 6 6x 1 k 4 6x 0.05 c j j1 a 0.10 c b1 b 0.05 c l2 note 5 l2 j j1 0.51 0.61 2.00 bsc 1.00 1.20 2.00 bsc 1.10 1.30 0.65 bsc 0.20 0.30 0.20 0.30 bottom view mounting footprint* recommended dimensions: millimeters l1 detail a l optional constructions ?? ??? ??? 6x 0.43 2.30 1.10 0.66 1.25 0.65 pitch 6x 0.35 1 package outline 0.35 0.34 0.60 l1 --- 0.10 top view detail b side view detail a a *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nvlus4c12n/d cool is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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